F SYSU FPGA Course Digital IC · HLS
Course ZedBoard HLS Resources Errata
中文 EN
GitHub

Sections

Course 1. Preface
AX7010 2.1 Lab 1 2.2 Experiment 2 2.4 Experiment 4
ZedBoard 3.1 Experiment 1 3.2 Experiment 2 3.3 Experiment 3 3.4 Experiment 4 3.5 Experiment 5 3.6 Experiment 6
HLS 4.1 Experiment 1 4.2 Experiment 2 4.3 Experiment 3 4.4 Experiment 4
Course Design 5. Course Design
Errata Errata
Resources Resources
Course Design

5. Course Design

5. Course Design

EN course-design

5. Course Design

  • Remove personal information from the course report and upload it with a clear summary of the work

The course design has been organized and completed. The report has been anonymized, and the related HLS / Notebook files remain under finial_product/.

Open the anonymized course report PDF

Open the anonymized course report PDF
← 4.4 Experiment 4 Errata →
SYSU FPGA Course · GitHub Pages 2026