2.1 Lab 1
2.1 Lab 1
2.1 Lab 1
Important Document: Lab 1 Manual
The detailed steps are provided in the PDF above. In this project, the main goal is to modify the three files labX.v, lab1_tb.v, and lab1.xdc to adapt them to the specific board.
The three files correspond to Verilog code, Testbench code, and constraints, respectively:
labX.v: Hardware descriptionlab1_tb.v: Simulationlab1.xdc: Constraints
Lab Results:
The following images and animation show the results of the experiment:
Behavioral Simulation
Project Summary
Schematic after Synthesis
Device Implementation
Post-Timing Simulation
Final Test
