| datasheet/AVNET Zedboard/底板原理图.pdf |
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| datasheet/AVNET Zedboard/核心板原理图.pdf |
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487.3 KB |
| datasheet/AVNET Zedboard/上手手册（手把手）.pdf |
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4.8 MB |
| datasheet/AVNET Zedboard/zedbaord 原理图.pdf |
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2.9 MB |
| datasheet/AVNET Zedboard/ZedBoard Zynq-7000 ARM FPGA进阶级处理器 全可编程逻辑智能互联开发系统 用户手册.pdf |
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2.4 MB |
| datasheet/AVNET Zedboard/zedboard 用户硬件手册.pdf |
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941.3 KB |
| datasheet/AVNET Zedboard/ZedBoard_Schematic.pdf |
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2.9 MB |
| datasheet/AVNET Zedboard/zedboard上手手册.pdf |
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2.7 MB |
| datasheet/AX7010开发板原理图.pdf |
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311.3 KB |
| datasheet/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf |
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1.2 MB |
| datasheet/High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS/Vitis/Lab1.pdf |
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1.0 MB |
| datasheet/lab1.pdf |
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1.1 MB |
| datasheet/lab2.pdf |
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624.6 KB |
| datasheet/lab3.pdf |
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626.0 KB |
| datasheet/lab4.pdf |
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573.5 KB |
| datasheet/lab5.pdf |
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1.4 MB |
| datasheet/lab6.pdf |
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449.7 KB |
| datasheet/ug480_7Series_XADC.pdf |
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2.9 MB |
| datasheet/ug585-Zynq-7000-TRM.pdf |
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42.4 MB |
| datasheet/ug821-zynq-7000-swdev.pdf |
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1.4 MB |
| datasheet/ug865-Zynq-7000-Pkg-Pinout.pdf |
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7.1 MB |
| datasheet/ug933-Zynq-7000-PCB.pdf |
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2.7 MB |
| finial_product/course_design_report_anonymized.pdf |
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3.8 MB |
| images/err_test.gif |
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| images/Figure1.jpg |
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| images/lab1/behavioral_sim.jpg |
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| images/lab1/finish.gif |
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| images/lab1/imp_device.jpg |
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| images/lab1/post_timing_sim.jpg |
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| images/lab1/project_summary.jpg |
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| images/lab1/syn_schematic.jpg |
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| images/my_board.jpg |
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2.7 MB |
| images/uart_link.jpg |
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2.5 MB |
| images/ZedBoard.jpg |
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2.6 MB |
| images/ZedBoard/lab_1/behavioral_simulation.jpg |
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| images/ZedBoard/lab_1/device.jpg |
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| images/ZedBoard/lab_1/post_timing_sim.jpg |
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| images/ZedBoard/lab_1/project_summary.jpg |
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| images/ZedBoard/lab_1/schematic.jpg |
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| images/ZedBoard/lab_1/test.gif |
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| images/ZedBoard/lab_2/checkpoint_file.jpg |
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| images/ZedBoard/lab_2/device.jpg |
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| images/ZedBoard/lab_2/final.gif |
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| images/ZedBoard/lab_2/power_report.jpg |
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| images/ZedBoard/lab_2/project_summary.jpg |
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| images/ZedBoard/lab_2/schematic_after_full.jpg |
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| images/ZedBoard/lab_2/schematic.jpg |
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| images/ZedBoard/lab_2/timing_summary.jpg |
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| images/ZedBoard/lab_3/clk_path.png |
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| images/ZedBoard/lab_3/device_path.jpg |
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| images/ZedBoard/lab_3/output_data_path.jpg |
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| images/ZedBoard/lab_3/project_summary.jpg |
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| images/ZedBoard/lab_3/timing_after_change_imp.jpg |
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| images/ZedBoard/lab_3/timing_after_change.jpg |
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| images/ZedBoard/lab_3/timing_report_imp.jpg |
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| images/ZedBoard/lab_3/timing_report.jpg |
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| images/ZedBoard/lab_4/char_fifo_after.jpg |
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| images/ZedBoard/lab_4/char_fifo_before.jpg |
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| images/ZedBoard/lab_4/device_&_utilization.jpg |
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| images/ZedBoard/lab_4/error.jpg |
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| images/ZedBoard/lab_4/final_test.png |
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| images/ZedBoard/lab_4/ip_clk_summary.jpg |
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| images/ZedBoard/lab_4/lock_reason.jpg |
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| images/ZedBoard/lab_4/step_not_need.jpg |
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| images/ZedBoard/lab_5/finish_all_setting.jpg |
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| images/ZedBoard/lab_5/path11.jpg |
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| images/ZedBoard/lab_5/Y9_pin.jpg |
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| images/ZedBoard/lab_6/debug_path.jpg |
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| images/ZedBoard/lab_6/wait_for_trigger.jpg |
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